This section provides an overview of the EXECUTION CORE functional block, the primary component of the processor.
• For details on the instruction set and local hardware devices, see 'Software » ISA Specification'
• For details on memory bus timing and operation, see 'Design » Bus Specifications'
The main system memory bus operates on a 64-bit address with 16-bit data. In addition to the primary address, there is a 2-bit memory 'region' which effectively extends the address to 66 bits; the MBUS_ADDRESS_REGION selects between four endpoints on the memory bus (similar to the X86 I/O M_IO pin and I/O instructions) and can be set by the core through the ADDRES_REGION register.
• MBUS_ADDRESS[63:0] - Output from core, primary address bus.
• MBUS_ADDRESS_REGION[1:0] - Output from core, selects active memory device.
• MBUS_DATA_D[15:0] - Input to core, primary data bus.
• MBUS_DATA_Q[15:0] - Output from core, primary data bus.
• MBUS_WRITE_READ_N - Output from core, controls whether data is being read from or written to memory.
• MBUS_ADDRESS_VALID - Output from core, flow control indicates that the bus request is valid.
• MBUS_DATA_VALID - Input to core, flow control indicates that data is ready on the bus.
The interrupt controller encodes an arbitrary number of interrupt lines (the current implementation has five interrupt lines available) into a queue of interrupt identifiers which is presented to the processor core. Interrupts are latched on the rising edge of the corresponding IREQ input
• IREQ - Input from interrupt controller, indicating that an active interrupt is waiting.
• IREQ_IDENT[15:0] - Input from interrupt controller, front of interrupt identifier queue.
• IREQ_ACK - Output to interrupt controller, dequeues the last active interrupt.
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