Processor FPGA Top Level

  • FPGA Top Level

    This block diagram provides a high level overview of the processor FPGA and its component functional units described below.

    Supporting circuitry and components (system clock, reset, power management, etc) not shown here; refer to the 'Hardware' section for more detail on implementation.

Functional Blocks
  • EXECUTION CORE

    Processor core. Refer to 'Execution Core' for more detail.

  • SRAM INTERFACE

    Primary system memory controller; provides a basic interface to a bank of external asynchronous SRAM ICs, primarily to handle data/address setup and bus turnaround timing requirements.

    Interfaces with the system memory bus at memory region 0b00.

  • INTERRUPT CONTROLLER

    Provides basic priority encoding of an arbitrary number of interrupt lines. Interrupt lines are encoded into a unique interrupt identifier (IREQ_IDENT); the interrupt identifier is loaded into a FIFO on the rising edge of the corresponding interrupt line. This FIFO can be read by the execution core during ISR execution to identify the source of the interrupt.

  • LOCAL PERIPHERAL BUS BRIDGE

    Provides a bridge between the system memory bus and the local peripheral bus. The system memory bus operates on a 64-bit address (MBUS_ADDRESS) which is translated into a 56-bit address used by the LPB, with the uppermost eight bits being repurposed into a device address used to select the targeted local peripheral bus device.

    Interfaces with the system memory bus at memory region 0b10.

  • REMOTE PERIPHERAL BUS INTERFACE

    Bidirectional serial interface to offboard devices. Refer to 'Remote Peripheral Bus' for more detail.

    Interfaces with the system memory bus at memory region 0b11.

  • FIRST STAGE BOOTLOADER

    A basic ROM attached to the system memory bus which contains the first stage bootloader, which is responsible for dumping the second stage loader from the EEPROM INTERFACE device on the LPB into system memory.

    Interfaces with the system memory bus at memory region 0b01.

  • HARDWARE ID

    Local peripheral bus device, provides a block of ROM containing hardware identification fields such as processor revision, instruction set support, etc.

  • EVENT TIMER

    Local peripheral bus device, provides a programmable timer with interrupt.

  • EEPROM INTERFACE

    Local peripheral bus device, provides an I2C serial interface to the second stage bootloader ROM.

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